International Science Index


10011953

Impact of Gate Insulation Material and Thickness on Pocket Implanted MOS Device

Abstract:This paper reports on the impact study with the variation of the gate insulation material and thickness on different models of pocket implanted sub-100 nm n-MOS device. The gate materials used here are silicon dioxide (SiO2), aluminum silicate (Al2SiO5), silicon nitride (Si3N4), alumina (Al2O3), hafnium silicate (HfSiO4), tantalum pentoxide (Ta2O5), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and lanthanum oxide (La2O3) upon a p-type silicon substrate material. The gate insulation thickness was varied from 2.0 nm to 3.5 nm for a 50 nm channel length pocket implanted n-MOSFET. There are several models available for this device. We have studied and simulated threshold voltage model incorporating drain and substrate bias effects, surface potential, inversion layer charge, pinch-off voltage, effective electric field, inversion layer mobility, and subthreshold drain current models based on two linear symmetric pocket doping profiles. We have changed the values of the two parameters, viz. gate insulation material and thickness gradually fixing the other parameter at their typical values. Then we compared and analyzed the simulation results. This study would be helpful for the nano-scaled MOS device designers for various applications to predict the device behavior.
References:
[1] A. Hokazono, S. Balasubramanian, K. Ishimaru, H. Ishiuchi, H. Chenming and L. T.-J. King, “MOSFET hot-carrier reliability improvement by forward-body bias,” IEEE Electron Device Letters, vol. 27, no. 7, pp. 605-608, July 2006.
[2] B. Yu, C. H. Wann, E. D. Nowak, K. Noda and C. Hu, “Short Channel Effect improved by lateral channel engineering in deep-submicrometer MOSFETs,” IEEE Transactions on Electron Devices, vol. 44, pp. 627-633, Apr. 1997.
[3] B. Yu, H. Wang, O. Millic, Q. Xiang, W. Wang, J. X. An and M. R. Lin, “50 nm gate length CMOS transistor with super-halo: Design, process and reliability,” IEEE IEDM Technical Digest, pp. 653-656, 1999.
[4] Y. S. Pang and J. R. Brews, “Models for subthreshold and above subthreshold currents in 0.1 m pocket n-MOSFETs for low voltage applications,” IEEE Transactions on Electron Devices, vol. 49, no. 5, pp. 832-839, May 2002.
[5] M. K. Khanna, M. C. Thomas, R. S. Gupta and S. Haldar, “An analytical model for anomalous threshold voltage behavior of short-channel MOSFETs,” Solid-State Electronics, vol. 41, pp. 1386-1388, 1997.
[6] H. Brut, A. Juge, and G. Ghibaudo, “Physical model of threshold voltage in silicon MOS transistors including reverse short channel effect,” Electronics Letters, vol. 31, no. 5, pp. 410-12, March 1995.
[7] M. H. Bhuyan and Q. D. M. Khosru, “Low-Frequency Drain Current Flicker Noise Model for Pocket Implanted Nano Scale n-MOSFET,” Proceedings of the IEEE and EDS sponsored Nano Materials and Device Conference (NMDC), 12-15 October 2010, CA, USA, pp. 295-299.
[8] M. H. Bhuyan and Q. D. M. Khosru, “An analytical surface potential model for pocket implanted sub-100 nm n-MOSFET,” Proceedings of the 5th IEEE International Conference on Electrical and Computer Engineering, Dhaka, 20-22 December 2008, pp 442-446.
[9] M. H. Bhuyan and Q. D. M. Khosru, “Linear pocket profile based threshold voltage model for sub-100 nm n-MOSFET,” International Journal of Electrical and Computer Engineering, vol. 5, no. 5, pp. 310-315, May 2010.
[10] M. H. Bhuyan, “Analytical modeling of the pocket implanted nanoscale n-MOSFET,” PhD Thesis, Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology, Dhaka, Bangladesh, 2011.
[11] M. H. Bhuyan and Q. D. M. Khosru, “An analytical subthreshold drain current model for pocket implanted nanoscale n-MOSFET,” Journal of Electron Devices, ISSN 1682-3427, vol. 8, pp 263-267, October 2010.
[12] M. H. Bhuyan, F. Ferdous and Q. D. M. Khosru, “A threshold voltage model for sub-100 nm pocket implanted NMOSFET,” Proceedings of the 4th IEEE International Conference on Electrical and Computer Engineering, Dhaka, Bangladesh, 19-21 December 2006, pp. 522-525.
[13] X. Zhou, K. Y. Lim and D. Lim, “Physics-Based threshold voltage modeling with Reverse Short Channel Effect,” Journal of Modeling and Simulation of Microsystems, Vol. 2, No. 1, pp. 51-56, 1999.
[14] X. Zhou, K. Y. Lim and D. Lim, “A general approach to compact threshold voltage formulation based on 2-D numerical simulation and experimental correlation for deep-submicron ULSI technology development,” IEEE Trans. on Electron Devices, vol. 47, no. 1, pp. 214-221, Jan. 2000.
[15] A. Mondal, A. Roy, R. Mitra and A. Kundu, “Comparative Study of Variations in Gate Oxide Material of a Novel Underlap DG MOS-HEMT for Analog/RF and High Power Applications,” Silicon, Springer, vol. 12, pp. 2251–2257, 2020.
[16] A. A. Sayem, Y. Arafat and M. M. Rahman, “Effect of High k-Dielectric as Gate Oxide on Short Channel Effects of Junction-less Transistor,” Proceedings of the 2nd IEEE International Conference on Advances in Electrical Engineering (ICAEE 2013), 19-21 December 2013, Dhaka, Bangladesh, pp. 115-118.
[17] J. Robertson and R. M. Wallace, “High-K materials and metal gates for CMOS applications,” Journal of Materials Science and Engineering R, vol. 88, 2015, pp. 1-41.
[18] G. Sethi, M. Olszta, J. Li, J. Sloppy, M. W. Horn, E. C. Dickey and M. T. Lanagan, “Structure and dielectric properties of amorphous tantalum pentoxide thin film capacitors,” 2007 Annual Report Conference on Electrical Insulation and Dielectric Phenomena, pp. 815-818.
[19] K. Koley, A. Dutta, B. Syamal, S. K. Saha, C. K. Sarkar, “Subthreshold analog/RF performance enhancement of underlap DG FETs with high- k spacer for low power applications,” IEEE Transaction on Electron Devices, vol. 60, no. 1, pp, 63-69, 2013.
[20] M. H. Bhuyan and Q. D. M. Khosru, “Linear Profile Based Analytical Surface Potential Model for Pocket Implanted Sub-100 nm n-MOSFET,” Journal of Electron Devices, France, 1682-3427, vol. 7, April 2010, pp 235-240.
[21] M. H. Bhuyan and Q. D. M. Khosru, “Linear Pocket Profile Based Pinch Off Voltage Model for Nanoscale n-MOSFET,” Proceedings of the 2nd IEEE International Conference on Electrical, Computer and Telecommunication Engineering (ICECTE 2016), Rajshahi University of Engineering and Technology (RUET), Rajshahi, Bangladesh, 8-10 December 2016, pp. 1-4, doi: 10.1109/ICECTE.2016.7879624.
[22] M. H. Bhuyan and Q. D. M. Khosru, “Inversion Layer Effective Mobility Model for Pocket Implanted Nano Scale n-MOSFET,” International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering, ISSN: p:2010-376X, e:2010-3778, vol. 5, no. 1, 2011, pp. 1-8.
[23] M. H. Bhuyan and Q. D. M. Khosru, “Analytical Subthreshold Drain Current Model Incorporating Inversion Layer Effective Mobility Model for Pocket Implanted Nano Scale n-MOSFET,” International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering, ISSN: p: 2010-376X, e: 2010-3778 vol. 7, no. 4, 2013, pp. 465 - 472.