International Science Index


234

A Low-cost Reconfigurable Architecture for AES Algorithm

Abstract:This paper proposes a low-cost reconfigurable architecture for AES algorithm. The proposed architecture separates SubBytes and MixColumns into two parallel data path, and supports different bit-width operation for this two data path. As a result, different number of S-box can be supported in this architecture. The throughput and power consumption can be adjusted by changing the number of S-box running in this design. Using the TSMC 0.18μm CMOS standard cell library, a very low-cost implementation of 7K Gates is obtained under 182MHz frequency. The maximum throughput is 360Mbps while using 4 S-Box simultaneously, and the minimum throughput is 114Mbps while only using 1 S-Box
References:
[1] National Institute of Standards and Technology (U.S.). Advanced Encryption Standards (AES). FIPS Publication 197, 2001.
[2] A. Satoh, S. Morioka, K. Takano, S. Munetoh, "A Compact Rijndael Hardware Architecture with S-Box Optimization," Advances in Cryptology - ASIACRYPT 2001, 7th International Conference on the Theory and Application of Cryptology and Information Security, Gold Coast, Australia, December 9-13, 2001, pp.239 - 254.
[3] D. Canright, "A Very Compact S-Box for AES," Cryptographic Hardware and Embedded Systems - CHES, September, 2005, pp.441 - 455.
[4] M. Feldhofer, S. Dominikus, J. Wolkerstorfer, " Strong Authentication for RFID Systems Using the AES Algorithm," Cryptographic Hardware and Embedded Systems - CHES 2004, Volume 3156, pp.357-370.
[5] S. Morioka, A. Satoh, "An Optimization S-Box Circuit Architecture for Low Power AES Design", CHES 2002, LNCS 2523, pp. 172-186.
[6] Jia Zhao, Xiaoyang Zeng, Jun Han, Jun Chen, "Very Low-cost VLSI Implementation of AES Algorithm", IEEE Asian Solid-State Circuits Conference, 2006, pp. 223 - 226.
[7] Norbert Pramstaller, Stefan Mangard, Sandra Dominikus, and Johannes Wolkerstorfer, "Efficient AES Implementations on ASICs and FPGAs", Proceedings of the Fourth Workshop on the Advanced Encryption Standard, AES4- State of the Crypto Analysis, LNCS vol- 3373 2005, pp. 98 - 112.